Charge pumps are well know circuits that are used to generate a “pumped voltage” that having a magnitude that is larger than the magnitude of a supply voltage. Normally the supply voltage is used to power most of the circuits in an integrated circuit, and the pumped voltage is used to power a relatively few of the circuits in the integrated circuit. For example, pumped voltages are commonly used to supply power to word line drivers and output buffers in integrated circuit dynamic random access memory (“DRAM”) devices, although the remaining circuitry in the DRAM is powered by a supply voltage. When used to power word line drivers and output buffers, the pumped voltage allows NMOS transistors in those circuits to pass the full magnitude of the supply voltage. Charge pumps are also used to generate voltages that have a polarity that is opposite the polarity of a supply voltage. For example, in a DRAM device powered by a positive supply voltage, a charge pump is often used to generate a negative voltage that is used to negatively bias either the substrate of the integrated circuit or a well fabricated in the integrated circuit. Biasing the substrate or well negatively reduces the leakage current of NMOS transistors in their OFF condition.
The principle of operation of conventional charge pumps is illustrated in FIGS. 1A and 1B. As shown in FIG. 1A, a capacitor 10 has first and second plates 12, 14, respectively, separated from each other by a dielectric. The first plate 12 of the capacitor 10 is coupled to suitable circuitry (not shown) that drives the first plate to a relatively low voltage, such as 0 volts, in a phase of operation. The second plate 14 of the capacitor 10 is also coupled to suitable circuitry (not shown) that charges the capacitor 10 in the first phase so that the voltage on the second plate 14 rises to a suitable voltage, such as the supply voltage VCC.
In a second phase of operation, the circuitry (not shown) coupled to the second plate 14 drives the second plate 14 to a suitable voltage, such as VCC, as shown in FIG. 1B. As a result, the voltage of the first plate 12 increases to twice VCC. This voltage 2VCC on the second plate is then coupled to an output node 20 through a suitable switching device, which is normally an NMOS transistor 22. The NMOS transistor 22 is normally turned ON to couple the plate 14 to the output node 20 by coupling the gate and drain of the transistor 22 to each other in a diode-coupled arrangement. As is well known in the art, a voltage coupled through a diode coupled transistor is reduced by a threshold voltage VT, which is typically about 0.7 volts. Thus, in practice, the pumped voltage applied to the output node 20 is 2VCC−VT.
The circuitry shown in FIG. 1B is known as a “charge pump stage,” and, as explained above, it is able to generated a pumped voltage of 2VCC−VT. A single charge pump stage shown in FIGS. 1A and 1B is suitable in some applications. However, in many applications, a pumped voltage having a magnitude greater than 2VCC−VT is required. This larger voltage can be provided by coupling multiple charge pump stages of the type shown in FIGS. 1A and 1B to each other in a “cascading” topography in which the pumped voltage from each charge pump stages is boosted by the subsequent charge pump stage. For example, in a three-stage charge pump, the first stage increases a supply voltage VCC to 2VCC−VT, as previously explained, the second stage increases that voltage to 3VCC−2VT, and the third stage increases that voltage to 4VCC−3VT. For a typical VCC of 3 volts and a typical VT of 0.7 volts, the three-stage charge pump can produce a pumped voltage of 9.9 volts ((4*3)−(3*0.7)).
Although a multiple stage charge pump can produce relatively large voltages, it does so at the price of very poor efficiency. As is well known in the art, the efficiency “E” of a multiple stage charge pump is given by the formula E=1/(N+1), where “N” is the number of stages in the charge pump. The efficiency of a one-stage charge pump is thus 50%, the efficiency of a two-stage charge pump is 33%, the efficiency of a three-stage charge pump is 25%, etc. While this relatively low efficiency is acceptable in some applications, it can be a substantial problem in many other applications. For example, in battery-powered portable devices, such as notebook personal computers, the inefficiency of multiple-stage charge pumps can significantly reduce the time the devices can be used before a battery recharge is needed.
There is therefore a need for a charge pump circuit and method that can produce a pumped voltage greater than can be achieved with a single stage charge pump with significantly higher efficiencies than can be achieved with multiple-stage charge pumps.